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1/27 l6208 september 2003 n operating supply voltage from 8 to 52v n 5.6a output peak current (2.8a rms) n r ds(on) 0.3 w typ. value @ t j = 25c n operating frequency up to 100khz n non dissipative overcurrent protection n dual independent constant t off pwm current controllers n fast/slow decay mode selection n fast decay quasi-synchronous rectification n decoding logic for stepper motor full and half step drive n cross conduction protection n thermal shutdown n under voltage lockout n integrated fast free wheeling diodes typical applications n bipolar stepper motor description the l6208 is a dmos fully integrated stepper motor driver with non-dissipative overcurrent protection, realized in multipower-bcd technology, which com- bines isolated dmos power transistors with cmos and bipolar circuits on the same chip. the device in- cludes all the circuitry needed to drive a two-phase bipolar stepper motor including: a dual dmos full bridge, the constant off time pwm current controller that performs the chopping regulation and the phase sequence generator, that generates the stepping sequence. available in powerdip24 (20+2+2), powerso36 and so24 (20+2+2) packages, the l6208 features a non-dissipative overcurrent protec- tion on the high side power mosfets and thermal shutdown. block diagram gate logic stepping sequence generation over current detection over current detection gate logic vcp vboot en control cw/ccw vref a v boot 5v 10v vs a vs b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator one shot monostable masking time thermal protection v boot v boot ocd b ocd a 10v 10v bridge a sense comparator bridge b d01in1225 rc a + - sense b vref b rc b half/full clock reset pwm ordering numbers: l6208n (powerdip24) l6208pd (powerso36) l6208d (so24) powerdip24 (20+2+2) powerso36 so24 (20+2+2) dmos driver for bipolar stepper motor
l6208 2/27 absolute maximum ratings recommended operating conditions symbol parameter test conditions value unit v s supply voltage v sa = v sb = v s 60 v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s = 60v; v sensea = v senseb = gnd 60 v v boot bootstrap peak voltage v sa = v sb = v s v s + 10 v v in ,v en input and enable voltage range -0.3 to +7 v v refa , v refb voltage range at pins v refa and v refb -0.3 to +7 v v rca, v rcb voltage range at pins rc a and rc b -0.3 to +7 v v sensea, v senseb voltage range at pins sense a and sense b -1 to +4 v i s(peak) pulsed supply current (for each v s pin), internally limited by the overcurrent protection v sa = v sb = v s ; t pulse < 1ms 7.1 a i s rms supply current (for each v s pin) v sa = v sb = v s 2.8 a t stg , t op storage and operating temperature range -40 to 150 c symbol parameter test conditions min max unit v s supply voltage v sa = v sb = v s 852v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s ; v sensea = v senseb 52 v v refa , v refb voltage range at pins v refa and v refb -0.1 5 v v sensea, v senseb voltage range at pins sense a and sense b (pulsed t w < t rr ) (dc) -6 -1 6 1 v v i out rms output current 2.8 a t j operating junction temperature -25 +125 c f sw switching frequency 100 khz
3/27 l6208 thermal data pin connections (top view) (5) the slug is internally connected to pins 1,18,19 and 36 (gnd pins). symbol description powerdip24 so24 powerso36 unit r th-j-pins maximum thermal resistance junction-pins 18 14 - c/w r th-j-case maximum thermal resistance junction-case - - 1 c/w r th-j-amb1 maximum thermal resistance junction-ambient (1) (1) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the bottom side of 6cm 2 (with a thickness of 35m). 43 51 - c/w r th-j-amb1 maximum thermal resistance junction-ambient (2) (2) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the top side of 6cm 2 (with a thickness of 35m). --35 c/w r th-j-amb1 maximum thermal resistance junction-ambient (3) (3) mounted on a multi-layer fr4 pcb with a dissipating copper surface on the top side of 6cm 2 (with a thickness of 35m), 16 via holes and a ground layer. --15 c/w r th-j-amb2 maximum thermal resistance junction-ambient (4) (4) mounted on a multi-layer fr4 pcb without any heat sinking surface on the board. 58 77 62 c/w gnd gnd out1 b rc b sense b half/full vref b 1 3 2 4 5 6 7 8 9 control vboot en out2 b vs b gnd gnd 19 18 17 16 15 13 14 d99in1083 10 11 12 24 23 22 21 20 clock cw/ccw sense a rc a out1 a vs a out2 a vcp reset vref a gnd n.c. n.c. vs a rc a out1 a n.c. n.c. n.c. n.c. n.c. out1 b rc b n.c. vs b n.c. n.c. gnd 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 gnd gnd d99in1084 clock sense a cw/ccw sense b half/full vref b 9 8 7 28 29 30 vref a control 10 27 out2 a reset vcp en out2 b vboot 14 12 11 23 25 26 n.c. n.c. 13 24 powerdip24/so24 powerso36 (5)
l6208 4/27 pin description package name type function so24/ powerdip24 powerso36 pin # pin # 1 10 clock logic input step clock input. the state machine makes one step on each rising edge. 2 11 cw/ccw logic input selects the direction of the rotation. high logic level sets clockwise direction, whereas low logic level sets counterclockwise direction. if not used, it has to be connected to gnd or +5v. 3 12 sense a power supply bridge a source pin. this pin must be connected to power ground through a sensing power resistor. 413rc a rc pin rc network pin. a parallel rc network connected between this pin and ground sets the current controller off-time of the bridge a. 5 15 out1 a power output bridge a output 1. 6, 7, 18, 19 1, 18, 19, 36 gnd gnd ground terminals. in powerdip24 and so24 packages, these pins are also used for heat dissipation toward the pcb. on powerso36 package the slug is connected to these pins. 8 22 out1 b power output bridge b output 1. 924rc b rc pin rc network pin. a parallel rc network connected between this pin and ground sets the current controller off-time of the bridge b. 10 25 sense b power supply bridge b source pin. this pin must be connected to power ground through a sensing power resistor. 11 26 vref b analog input bridge b current controller reference voltage. do not leave this pin open or connected to gnd. 12 27 half/full logic input step mode selector. high logic level sets half step mode, low logic level sets full step mode. if not used, it has to be connected to gnd or +5v. 13 28 control logic input decay mode selector. high logic level sets slow decay mode. low logic level sets fast decay mode. if not used, it has to be connected to gnd or +5v. 14 29 en logic input (6) chip enable. low logic level switches off all power mosfets of both bridge a and bridge b. this pin is also connected to the collector of the overcurrent and thermal protection to implement over current protection. if not used, it has to be connected to +5v through a resistor. 15 30 vboot supply voltage bootstrap voltage needed for driving the upper power mosfets of both bridge a and bridge b. 16 32 out2 b power output bridge b output 2. 17 33 vs b power supply bridge b power supply voltage. it must be connected to the supply voltage together with pin vs a 20 4 vs a power supply bridge a power supply voltage. it must be connected to the supply voltage together with pin vs b
5/27 l6208 (6) also connected at the output drain of the over current and thermal protection mosfet. therefore, it has to be driven puttin g in series a resistor with a value in the range of 2.2k w - 180k w , recommended 100k w. package name type function so24/ powerdip24 powerso36 pin # pin # 21 5 out2 a power output bridge a output 2. 22 7 vcp output charge pump oscillator output. 23 8 reset logic input reset pin. low logic level restores the home state (state 1) on the phase sequence generator state machine. if not used, it has to be connected to +5v. 24 9 vref a analog input bridge a current controller reference voltage. do not leave this pin open or connected to gnd. electrical characteristics (t amb = 25c, v s = 48v, unless otherwise specified) symbol parameter test conditions min typ max unit v sth(on) turn-on threshold 6.6 7 7.4 v v sth(off) turn-off threshold 5.6 6 6.4 v i s quiescent supply current all bridges off; t j = -25c to 125c (7) 510ma t j(off) thermal shutdown temperature 165 c output dmos transistors r ds(on) high-side switch on resistance t j = 25 c 0.34 0.4 w t j =125 c (7) 0.53 0.59 w low-side switch on resistance t j = 25 c 0.28 0.34 w t j =125 c (7) 0.47 0.53 w i dss leakage current en = low; out = v s 2ma en = low; out = gnd -0.15 ma source drain diodes v sd forward on voltage i sd = 2.8a, en = low 1.15 1.3 v t rr reverse recovery time i f = 2.8a 300 ns t fr forward recovery time 200 ns logic inputs (en, control, half/full, clock, reset, cw/ccw) v il low level logic input voltage -0.3 0.8 v v ih high level logic input voltage 2 7 v pin description (continued)
l6208 6/27 i il low level logic input current gnd logic input voltage -10 a i ih high level logic input current 7v logic input voltage 10 a v th(on) turn-on input threshold 1.8 2.0 v v th(off) turn-off input threshold 0.8 1.3 v v th(hys) input threshold hysteresis 0.25 0.5 v switching characteristics t d(on)en enable to output turn-on delay time (8) i load =2.8a, resistive load 100 250 400 ns t d(off)en enable to output turn-off delay time (8) i load =2.8a, resistive load 300 550 800 ns t rise output rise time (8) i load =2.8a, resistive load 40 250 ns t fa ll output fall time (8) i load =2.8a, resistive load 40 250 ns t dclk clock to output delay time (9) i load =2.8a, resistive load 2 s t clk(min)l minimum clock time (10) 1s t clk(min) h minimum clock time (10) 1s f clk clock frequency 100 khz t s(min) minimum set-up time (11) 1s t h(min) minimum hold time (11) 1s t r(min) minimum reset time (11) 1s t rclk(min ) minimum reset to clock delay time (11) 1s t dt dead time protection 0.5 1 s f cp charge pump frequency t j = -25c to 125c (7) 0.6 1 mhz pwm comparator and monostable i rca, i rcb source current at pins rc a and rc b v rca = v rcb = 2.5v 3.5 5.5 ma v offset offset voltage on sense comparator v refa, v refb = 0.5v 5 mv t prop turn off propagation delay (12) 500 ns t blank internal blanking time on sense pins 1s t on(min) minimum on time 1.5 2 s electrical characteristics (continued) (t amb = 25c, v s = 48v, unless otherwise specified) symbol parameter test conditions min typ max unit
7/27 l6208 (7) tested at 25c in a restricted range and guaranteed by characterization. (8) see fig. 1. (9) see fig. 2. (10) see fig. 3. (11) see fig. 4. (12) measured applying a voltage of 1v to pin sense and a voltage drop from 2v to 0v to pin vref. (13) see fig. 5. figure 1. switching characteristic definition t off pwm recirculation time r off = 20k w; c off = 1nf 13 s r off = 100k w; c off = 1nf 61 s i bias input bias current at pins vref a and vref b 10 a over current protection i sover input supply overcurrent protection threshold t j = -25c to 125c (7) 4 5.6 7.1 a r opdr open drain on resistance i = 4ma 40 60 w t ocd(on) ocd turn-on delay time (13) i = 4ma; c en < 100pf 200 ns t ocd(off) ocd turn-off delay time (13) i = 4ma; c en < 100pf 100 ns electrical characteristics (continued) (t amb = 25c, v s = 48v, unless otherwise specified) symbol parameter test conditions min typ max unit v th(on) v th(off) 90% 10% en i out t t t fall t d(off)en t rise t d(on)en d01in1316
l6208 8/27 figure 2. clock to output delay time figure 3. minimum timing definition; clock input figure 4. minimum timing definition; logic inputs clock i out t t t dclk v th(on) d01in1317 clock t clk(min)h t clk(min)l v th(off) v th(on) d01in1318 v th(off) clock reset t s(min) t h(min) t r(min) t rclk(min) logic inputs d01in1319 v th(off) v th(on) v th(on)
9/27 l6208 figure 5. overcurrent detection timing definition circuit description power stages and charge pump the l6208 integrates two independent power mos full bridges. each power mos has an r ds(on) = 0.3 w (typ- ical value @ 25c), with intrinsic fast freewheeling diode. switching patterns are generated by the pwm current controller and the phase sequence generator (see below). cross conduction protection is achieved using a dead time (t dt = 1 m s typical value) between the switch off and switch on of two power mosfetss in one leg of a bridge. pins vs a and vs b must be connected together to the supply voltage v s . the device operates with a supply voltage in the range from 8v to 52v. it has to be noticed that the r ds(on) increases of some percents when the supply voltage is in the range from 8v to 12v (see fig. 34 and 35). using n-channel power mos for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped supply voltage v boot is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in figure 6. the oscillator output (vcp) is a square wave at 600khz (typical) with 10v amplitude. recommended values/part numbers for the charge pump circuit are shown in table 1. table 1. charge pump external components values c boot 220nf c p 10nf r p 100 w d1 1n4148 d2 1n4148 i sover 90% 10% i out v en t ocd(off) t ocd(on) d02in1399 on off bridge
l6208 10/27 figure 6. charge pump circuit logic inputs pins control, half/full, clock, reset and cw/ccw are ttl/cmos and uc compatible logic inputs. the internal structure is shown in fig. 7. typical value for turn-on and turn-off thresholds are respectively v th(on) = 1.8v and v th(off) = 1.3v. pin en (enable) has identical input structure with the exception that the drain of the overcurrent and thermal protection mosfet is also connected to this pin. due to this connection some care needs to be taken in driving this pin. the en input may be driven in one of two configurations as shown in fig. 8 or 9. if driven by an open drain (collector) structure, a pull-up resistor r en and a capacitor c en are connected as shown in fig. 8. if the driver is a standard push-pull structure the resistor r en and the capacitor c en are connected as shown in fig. 9. the resistor r en should be chosen in the range from 2.2k w to 180k w . recommended values for r en and c en are respectively 100k w and 5.6nf. more information on selecting the values is found in the overcurrent protection section. figure 7. logic inputs internal structure figure 8. en pin open collector driving figure 9. en pin push-pull driving d2 c boot d1 r p c p v s vs a vcp vboot vs b d01in1328 5v d01in1329 esd protection 5v 5v open collector output r en c en en d01in133 0 esd protection 5v push-pull output r en c en en d01in1331 esd protection
11/27 l6208 pwm current control the l6208 includes a constant off time pwm current controller for each of the two bridges. the current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be- tween the source of the two lower power mos transistors and ground, as shown in figure 10. as the current in the motor builds up the voltage across the sense resistor increases proportionally. when the voltage drop across the sense resistor becomes greater than the voltage at the reference input (vref a or vref b ) the sense comparator triggers the monostable switching the bridge off. the power mos remain off for the time set by the monostable and the motor current recirculates as defined by the selected decay mode, described in the next section. when the monostable times out the bridge will again turn on. since the internal dead time, used to pre- vent cross conduction in the bridge, delays the turn on of the power mos, the effective off time is the sum of the monostable time plus the dead time. figure 10. pwm current controller simplified schematic figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing re- sistor, the rc pin voltage and the status of the bridge. more details regarding the synchronous rectification and the output stage configuration are included in the next section. immediately after the power mos turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. the l6208 provides a 1 m s blanking time t blank that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable. drivers + dead time s q r drivers + dead time 2h 1h 2l 1l out2 a(or b) sense a(or b) r sense d01in1332 rc a(or b) r off c off vref a(or b) i out out1 a(or b) + + - - 1 m s 5ma blanker sense comparator comparator output monostable set 2.5v 5v from the low-side gate drivers 2 phase stepper motor blanking time monostable vs a (or b ) to gate logic (0) (1)
l6208 12/27 figure 11. output current regulation waveforms figure 12 shows the magnitude of the off time t off versus c off and r off values. it can be approximately calculated from the equations: t rcfall = 0.6 r off c off t off = t rcfall + t dt = 0.6 r off c off + t dt where r off and c off are the external component values and t dt is the internally generated dead time with: 20k w r off 100k w 0.47nf c off 100nf t dt = 1s (typical value) therefore: t off(min) = 6.6s t off(max) = 6ms these values allow a sufficient range of t off to implement the drive circuit for most motors. the capacitor value chosen for c off also affects the rise time t rcrise of the voltage at the pin rcoff. the rise time t rcrise will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. therefore, the on time t on , which depends by motors and supply parameters, has to be bigger than t rcrise for allowing a good current regulation by the pwm stage. furthermore, the on time t on can not be smaller than the minimum on time t on(min) . off bc dd a t on t off t off bc on 2.5v 0 fast decay fast decay slow decay slow decay 1 m s t blank t rcrise 1 m s t dt 1 m s t dt t rcrise t rcfall t rcfall synchronous or quasi synchronous rectification 1 m s t blank 5v v rc v sense v ref i out v ref r sense d01in1334
13/27 l6208 t rcrise = 600 c off figure 13 shows the lower limit for the on time t on for having a good pwm current regulation capacity. it has to be said that t on is always bigger than t on(min) because the device imposes this condition, but it can be smaller than t rcrise - t dt . in this last case the device continues to work but the off time t off is not more constant. so, small c off value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for c off , the more influential will be the noises on the circuit performance. figure 12. t off versus c off and r off figure 13. area where t on can vary maintaining the pwm regulation. t on t on min () >1.5 m s (typ. value) = t on t rcrise t dt C > ? ? ? 0.1 1 10 100 1 10 100 1 . 10 3 1 . 10 4 coff [nf] toff [ m s] r off = 100k w r off = 47k w r off = 20k w 0.1 1 10 100 1 10 100 coff [nf] ton(min) [ m s] 1.5 m s (typ. value)
l6208 14/27 decay modes the control input is used to select the behavior of the bridge during the off time. when the control pin is low, the fast decay mode is selected and both transistors in the bridge are switched off during the off time. when the control pin is high, the slow decay mode is selected and only the low side transistor of the bridge is switched off during the off time. figure 14 shows the operation of the bridge in the fast decay mode. at the start of the off time, both of the power mos are switched off and the current recirculates through the two opposite free wheeling diodes. the current decays with a high di/dt since the voltage across the coil is essentially the power supply voltage. after the dead time, the lower power mos in parallel with the conducting diode is turned on in synchronous rectifica- tion mode. in applications where the motor current is low it is possible that the current can decay completely to zero during the off time. at this point if both of the power mos were operating in the synchronous rectification mode it would then be possible for the current to build in the opposite direction. to prevent this only the lower power mos is operated in synchronous rectification mode. this operation is called quasi-synchronous recti- fication mode. when the monostable times out, the power mos are turned on again after some delay set by the dead time to prevent cross conduction. figure 15 shows the operation of the bridge in the slow decay mode. at the start of the off time, the lower power mos is switched off and the current recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slowly. after the dead time the upper power mos is operated in the synchro- nous rectification mode. when the monostable times out, the lower power mos is turned on again after some delay set by the dead time to prevent cross conduction. figure 14. fast decay mode output stage configurations figure 15. slow decay mode output stage configurations stepping sequence generation the phase sequence generator is a state machine that provides the phase and enable inputs for the two bridges to drive a stepper motor in either full step or half step. two full step modes are possible, the normal drive mode where both phases are energized each step and the wave drive mode where only one phase is energized at a a) on time b) 1 m s dead time c) quasi-synchronous rectification d) 1 m s slow decay d01in1335 a) on time b) 1 m s dead time c) synchronous rectification d) 1 m s dead time d01in1336
15/27 l6208 time. the drive mode is selected by the half/full input and the current state of the sequence generator as described below. a rising edge of the clock input advances the state machine to the next state. the direction of rotation is set by the cw/ccw input. the reset input resets the state machine to state. half step mode a high logic level on the half/full input selects half step mode. figure 16 shows the motor current wave- forms and the state diagram for the phase sequencer generator. at start-up or after a reset the phase se- quencer is at state 1. after each clock pulse the state changes following the sequence 1,2,3,4,5,6,7,8, if cw/ ccw is high (clockwise movement) or 1,8,7,6,5,4,3,2, if cw/ccw is low (counterclockwise movement). normal drive mode (full-step two-phase-on) a low level on the half/full input selects the full step mode. when the low level is applied when the state machine is at an odd numbered state the normal drive mode is selected. figure fig. 17 shows the motor cur- rent waveform state diagram for the state machine of the phase sequencer generator. the normal drive mode can easily be selected by holding the half/full input low and applying a reset. at start -up or after a re- set the state machine is in state1. while the half/full input is kept low, state changes following the se- quence 1,3,5,7, if cw/ccw is high (clockwise movement) or 1,7,5,3, if cw/ccw is low (counterclockwise movement). wave drive mode (full-step one-phase-on) a low level on the pin half/full input selects the full step mode. when the low level is applied when the state machine is at an even numbered state the wave drive mode is selected. figure 18 shows the motor cur- rent waveform and the state diagram for the state machine of the phase sequence generator. to enter the wave drive mode the state machine must be in an even numbered state. the most direct method to select the wave drive mode is to first apply a reset, then while keeping the half/full input high apply one pulse to the clock input then take the half/full input low. this sequence first forces the state machine to sate 1. the clock pulse, with the half/full input high advances the state machine from state 1 to either state 2 or 8 de- pending on the cw/ccw input. starting from this point, after each clock pulse (rising edge) will advance the state machine following the sequence 2,4,6,8, if cw/ccw is high (clockwise movement) or 8,6,4,2, if cw/ ccw is low (counterclockwise movement). figure 16. half step mode figure 17. normal drive mode 3 2 4 5 1 d01in1320 2345678 6 1 8 7 i outa i outb clock start up or reset 2 4 1 d01in1322 3571357 6 8 i outa i outb clock 35 17 start up or reset
l6208 16/27 figure 18. wave drive mode non-dissipative overcurrent protection the l6208 integrates an overcurrent detection circuit (ocd). this circuit provides protection against a short circuit to ground or between two phases of the bridge. with this internal over current detection, the external cur- rent sense resistor normally used and its associated power dissipation are eliminated. figure 19 shows a sim- plified schematic of the overcurrent detection circuit. to implement the over current detection, a sensing element that delivers a small but precise fraction of the out- put current is implemented with each high side power mos. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference cur- rent i ref . when the output current reaches the detection threshold (typically 5.6a) the ocd comparator signals a fault condition. when a fault condition is detected, the en pin is pulled below the turn off threshold (1.3v typ- ical) by an internal open drain mos with a pull down capability of 4ma. by using an external r-c on the en pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. figure 19. overcurrent protection simplified schematic 2 4 2 d01in1321 4682468 6 8 i outa i outb clock 35 17 start up or reset + over temperature i ref (i 1a +i 2a ) / n i 1a / n power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells high side dmoss of the bridge a out1 a out2 a vs a i 1a i 2a i 2a / n from the bridge b ocd comparator ocd comparator to gate logic internal open-drain r ds(on) 40 w typ. c en . r en .en v dd m c or logic d01in1337
17/27 l6208 figure 20 shows the overcurrent detection operation. the disable time t disable before recovering normal oper- ation can be easily programmed by means of the accurate thresholds of the logic inputs. it is affected whether by c en and r en values and its magnitude is reported in figure 21. the delay time t delay before turning off the bridge when an overcurrent has been detected depends only by c en value. its magnitude is reported in figure 22. c en is also used for providing immunity to pin en against fast transient noises. therefore the value of c en should be chosen as big as possible according to the maximum tolerable delay time and the r en value should be chosen according to the desired disable time. the resistor r en should be chosen in the range from 2.2k w to 180k w . recommended values for r en and c en are respectively 100k w and 5.6nf that allow obtaining 200 m s disable time. figure 20. overcurrent protection waveforms i sover i out v th(on) v th(off) v en(low) v dd t ocd(on) t d(on)en t en(fall) t en(rise) t disable t delay t ocd(off) t d(off)en v en bridge on off ocd on off d02in1400
l6208 18/27 figure 21. t disable versus c en and r en (v dd = 5v). figure 22. t delay versus c en (v dd = 5v). thermal protection in addition to the ovecurrent protection, the l6208 integrates a thermal protection for preventing the device destruction in case of junction over temperature. it works sensing the die temperature by means of a sensible element integrated in the die. the device switch-off when the junction temperature reaches 165c (typ. value) with 15c hysteresis (typ. value). 110100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k w r en = 100 k w r en = 47 k w r en = 33 k w r en = 10 k w 110100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k w r en = 100 k w r en = 47 k w r en = 33 k w r en = 10 k w 1 10 100 0.1 1 10 cen [nf] tdelay [ m s]
19/27 l6208 application information a typical bipolar stepper motor driver application using l6208 is shown in fig. 23. typical component values for the application are shown in table 2. a high quality ceramic capacitor in the range of 100 to 200 nf should be placed between the power pins (vs a and vs b ) and ground near the l6208 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitor connected from the en input to ground sets the shut down time when an over current is detected (see overcur- rent protection). the two current sensing inputs (sense a and sense b ) should be connected to the sensing resistors with a trace length as short as possible in the layout. the sense resistors should be non-inductive re- sistors to minimize the di/dt transients across the resistor. to increase noise immunity, unused logic pins (except en) are best connected to 5v (high logic level) or gnd (low logic level) (see pin description). it is recom- mended to keep power ground and signal ground separated on pcb. table 2. component values for typical application figure 23. typical application c 1 100f d 1 1n4148 c 2 100nf d 2 1n4148 c a 1nf r a 39k w c b 1nf r b 39k w c boot 220nf r en 100k w c p 10nf r p 100 w c en 5.6nf r sensea 0.3 w c ref 68nf r senseb 0.3 w m out1 a vref a vref b clock 1 5 21 18 19 8 16 out2 a gnd gnd gnd gnd rc a out2 b out1 b vs a power ground signal ground + - v s 8-52v dc 24 vs b vcp vboot c p c boot r p d 2 d 1 c 1 c 2 sense a r sensea 20 cw/ccw clock cw/ccw 2 6 7 11 reset en c en r en reset enable v ref = 0-1v 23 half/full half/full 12 control fast/slow decay 13 14 4 17 3 15 22 sense b r senseb c a r a 10 c ref rc b 9 c b r b d01in1341
l6208 20/27 output current capability and ic power dissipation in fig. 24, 25, 26 and 27 are shown the approximate relation between the output current and the ic power dis- sipation using pwm current control driving a two-phase stepper motor, for different driving sequences: C half step mode (fig. 24) in which alternately one phase / two phases are energized. C normal drive (full-step two phase on) m ode (fig. 25) in which two phases are energized during each step. C wave drive (full-step one phase on) mode (fig. 26) in which only one phase is energized at each step. C microstepping mode (fig. 27), in which the current follows a sine-wave profile, provided through the v ref pins. for a given output current and driving sequence the power dissipated by the ic can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guar- antee a safe operating junction temperature (125c maximum). figure 24. ic power dissipation versus output current in half step mode. figure 25. ic power dissipation versus output current in normal mode (full step two phase on). no pwm f sw = 30 khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 p d [w] i out [a ] half step no pwm f sw = 30 khz (slow decay) test conditions: supply volt age = 24 v i a i b i out i out 00.511.522.5 3 0 2 4 6 8 10 p d [w ] i out [a ] norm al drive
21/27 l6208 figure 26. ic power dissipation versus output current in wave mode (full step one phase on). figure 27. ic power dissipation versus output current in microstepping mode. thermal management in most applications the power dissipation in the ic is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. therefore, it has to be taken into account very carefully. besides the available space on the pcb, the right package should be chosen considering the power dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. figures 28, 29 and 30 show the junction-to-ambient thermal resistance values for the powerso36, powerdip24 and so24 packag- es. for instance, using a powerso package with copper slug soldered on a 1.5mm copper thickness fr4 board with 6cm 2 dissipating footprint (copper thickness of 35m), the r th(j-amb) is about 35c/w. fig. 31 shows mount- ing methods for this package. using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15c/w. no pwm f sw = 3 0 khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out wave drive 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 p d [w] i out [a] f sw = 50 k hz (slow decay) f sw = 30 k hz (slow decay) i a i b i out i out microstepping 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 p d [w] i out [a] test conditions: supply voltage = 24v
l6208 22/27 figure 28. powerso36 junction-ambient thermal resistance versus on-board copper area. figure 29. powerdip24 junction-ambient thermal resistance versus on-board copper area. figure 30. so24 junction-ambient thermal resistance versus on-board copper area. figure 31. mounting the powerso package. 13 18 23 28 33 38 43 12345678910111213 without ground layer with ground layer with ground layer+16 via holes sq. cm oc / w on-board copper area 39 40 41 42 43 44 45 46 47 48 49 1 2 3 4 5 6 7 8 9 101112 copper area is on bottom side copper area is on top side sq. cm oc / w on-board copper area 48 50 52 54 56 58 60 62 64 66 68 123456789101112 copper area is on top side sq. cm oc / w on-board copper area slug soldered to pcb with dissipating area slug soldered to pcb with dissipating area plus ground layer slug soldered to pcb with dissipating area plus ground layer contacted through via holes
23/27 l6208 figure 32. typical quiescent current vs. supply voltage figure 33. normalized typical quiescent current vs. switching frequency figure 34. typical low-side r ds(on) vs. supply voltage figure 35. typical high-side rds(on) vs. supply voltage figure 36. normalized r ds(on) vs.junction temperature (typical value) figure 37. typical drain-source diode forward on characteristic 4.6 4.8 5.0 5.2 5.4 5.6 0 102030405060 iq [ma] v s [v] f sw = 1khz t j = 25c t j = 85c t j = 125c 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0 20406080100 iq / (iq @ 1 khz) f sw [khz] 0.276 0.280 0.284 0.288 0.292 0.296 0.300 0 5 10 15 20 25 30 r ds(on) [ w ] v s [v] t j = 25c 0.336 0.340 0.344 0.348 0.352 0.356 0.360 0.364 0.368 0.372 0.376 0.380 0 5 10 15 20 25 30 r ds(on) [ w ] v s [v] t j = 25c 0.8 1.0 1.2 1.4 1.6 1.8 0 20406080100120140 r ds(on) / (r ds(on) @ 25 c) tj [c] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 700 800 900 1000 1100 1200 1300 i sd [a] v sd [mv] t j = 25c
l6208 24/27 dim. mm inch min. typ. max. min. typ. max. a 3.60 0.141 a1 0.10 0.30 0.004 0.012 a2 3.30 0.130 a3 0 0.10 0 0.004 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 d (1) 15.80 16.00 0.622 0.630 d1 9.40 9.80 0.370 0.385 e 13.90 14.50 0.547 0.570 e 0.65 0.0256 e3 11.05 0.435 e1 (1) 10.90 11.10 0.429 0.437 e2 2.90 0.114 e3 5.80 6.20 0.228 0.244 e4 2.90 3.20 0.114 0.126 g 0 0.10 0 0.004 h 15.50 15.90 0.610 0.626 h 1.10 0.043 l 0.80 1.10 0.031 0.043 n10 (max.) s8 (max.) (1): "d" and "e1" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - critical dimensions are "a3", "e" and "g". powerso36 e a2 a e a1 pso36mec detail a d 118 19 36 e1 e2 h x 45? detail a lead slug a3 s gage plane 0.35 l detail b detail b (coplanarity) gc - c - seating plane e3 c n n ? m 0.12 ab b b a h e3 d1 bottom view outline and mechanical data
25/27 l6208 dim. mm inch min. typ. max. min. typ. max. a 4.320 0.170 a1 0.380 0.015 a2 3.300 0.130 b 0.410 0.460 0.510 0.016 0.018 0.020 b1 1.400 1.520 1.650 0.055 0.060 0.065 c 0.200 0.250 0.300 0.008 0.010 0.012 d 31.62 31.75 31.88 1.245 1.250 1.255 e 7.620 8.260 0.300 0.325 e 2.54 0.100 e1 6.350 6.600 6.860 0.250 0.260 0.270 e1 7.620 0.300 l 3.180 3.430 0.125 0.135 m 0? min, 15? max. powerdip 24 a1 b e b1 d 13 12 24 1 l a e1 a2 c e1 sdip24l m outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 26/27 l6208 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.200 c 0.23 0.32 0.009 0.013 d (1) 15.20 15.60 0.598 0.614 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.25 0;75 0.010 0.030 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) d dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so24 0070769 c weight: 0.60gr
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 27/27 l6208

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